// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  hipciec_ap_mg_reg_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2017/10/24
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/16 18:03:14 Create file
// ******************************************************************************

#ifndef __HIPCIEC_AP_MG_REG_REG_OFFSET_FIELD_H__
#define __HIPCIEC_AP_MG_REG_REG_OFFSET_FIELD_H__

#define HIPCIEC_AP_MG_REG_PCIE_ERR_MAPPING_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_ERR_MAPPING_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_CE_ENA_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_CE_ENA_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_UNF_ENA_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_UNF_ENA_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_UF_ENA_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_UF_ENA_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_CE_STATUS_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_CE_STATUS_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_UNF_STATUS_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_UNF_STATUS_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_UF_STATUS_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_UF_STATUS_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_0_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_1_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_2_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_3_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_3_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_4_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_4_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_5_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_5_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_6_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_6_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_7_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_7_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_8_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_8_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_9_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_9_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_10_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_10_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_11_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_11_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_12_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_12_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_13_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_13_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_14_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_14_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_15_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_15_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_16_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_16_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_17_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_17_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_18_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_18_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_19_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_19_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_20_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_20_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_21_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_21_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_22_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_22_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_23_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_23_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_24_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_24_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_25_LEN    32
#define HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_25_OFFSET 0

#define HIPCIEC_AP_MG_REG_PCIE_LOCAL_ERR_TYPE_LEN    12
#define HIPCIEC_AP_MG_REG_PCIE_LOCAL_ERR_TYPE_OFFSET 0

#define HIPCIEC_AP_MG_REG_CFG_INTX_CLR_EN_LEN    20
#define HIPCIEC_AP_MG_REG_CFG_INTX_CLR_EN_OFFSET 0

#define HIPCIEC_AP_MG_REG_CFG_INTX_DEASSERT_MODE_LEN    20
#define HIPCIEC_AP_MG_REG_CFG_INTX_DEASSERT_MODE_OFFSET 0

#define HIPCIEC_AP_MG_REG_CFG_ODR_DISP_CTRL_LEN    12
#define HIPCIEC_AP_MG_REG_CFG_ODR_DISP_CTRL_OFFSET 0

#define HIPCIEC_AP_MG_REG_DFX_PORT_INTX_PENDING_CNT_LEN    9
#define HIPCIEC_AP_MG_REG_DFX_PORT_INTX_PENDING_CNT_OFFSET 0

#define HIPCIEC_AP_MG_REG_DFX_CORE_INTX_CNT_LEN    16
#define HIPCIEC_AP_MG_REG_DFX_CORE_INTX_CNT_OFFSET 0

#define HIPCIEC_AP_MG_REG_DFX_PORT_ERR_COR_CNT_LEN    16
#define HIPCIEC_AP_MG_REG_DFX_PORT_ERR_COR_CNT_OFFSET 0

#define HIPCIEC_AP_MG_REG_DFX_CORE_ERR_MSG_CNT_LEN    24
#define HIPCIEC_AP_MG_REG_DFX_CORE_ERR_MSG_CNT_OFFSET 0

#define HIPCIEC_AP_MG_REG_DFX_ODR_P_CNT_LEN    32
#define HIPCIEC_AP_MG_REG_DFX_ODR_P_CNT_OFFSET 0

#define HIPCIEC_AP_MG_REG_DFX_ODR_NP_CNT_LEN    16
#define HIPCIEC_AP_MG_REG_DFX_ODR_NP_CNT_OFFSET 0

#define HIPCIEC_AP_MG_REG_AP_RAM_TIMING_CFG0_LEN    32
#define HIPCIEC_AP_MG_REG_AP_RAM_TIMING_CFG0_OFFSET 0

#define HIPCIEC_AP_MG_REG_AP_RAM_TIMING_CFG1_LEN    32
#define HIPCIEC_AP_MG_REG_AP_RAM_TIMING_CFG1_OFFSET 0

#define HIPCIEC_AP_MG_REG_WORK_MODE_LEN    2
#define HIPCIEC_AP_MG_REG_WORK_MODE_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_RESET_0_LEN              1
#define HIPCIEC_AP_MG_REG_MCTP_RX_RESET_0_OFFSET           28
#define HIPCIEC_AP_MG_REG_MCTP_TX_RESET_0_LEN              1
#define HIPCIEC_AP_MG_REG_MCTP_TX_RESET_0_OFFSET           27
#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_EN_0_LEN            2
#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_EN_0_OFFSET         25
#define HIPCIEC_AP_MG_REG_MCTP_RSVD_PORT_NUM_0_LEN         5
#define HIPCIEC_AP_MG_REG_MCTP_RSVD_PORT_NUM_0_OFFSET      20
#define HIPCIEC_AP_MG_REG_MCTP_SUBSTITUTE_DROP_EN_0_LEN    2
#define HIPCIEC_AP_MG_REG_MCTP_SUBSTITUTE_DROP_EN_0_OFFSET 18
#define HIPCIEC_AP_MG_REG_MAX_PAYLOAD_SIZE_0_LEN           10
#define HIPCIEC_AP_MG_REG_MAX_PAYLOAD_SIZE_0_OFFSET        8
#define HIPCIEC_AP_MG_REG_MCTP_CFG_QUEUE_UNIT_0_LEN        3
#define HIPCIEC_AP_MG_REG_MCTP_CFG_QUEUE_UNIT_0_OFFSET     5
#define HIPCIEC_AP_MG_REG_MCTP_CFG_CHECK_EN_0_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_CFG_CHECK_EN_0_OFFSET       4
#define HIPCIEC_AP_MG_REG_MCTP_RX_EN_0_LEN                 1
#define HIPCIEC_AP_MG_REG_MCTP_RX_EN_0_OFFSET              3
#define HIPCIEC_AP_MG_REG_MCTP_RX_IF_EN_0_LEN              1
#define HIPCIEC_AP_MG_REG_MCTP_RX_IF_EN_0_OFFSET           2
#define HIPCIEC_AP_MG_REG_MCTP_TX_EN_0_LEN                 1
#define HIPCIEC_AP_MG_REG_MCTP_TX_EN_0_OFFSET              1
#define HIPCIEC_AP_MG_REG_MCTP_TX_IF_EN_0_LEN              1
#define HIPCIEC_AP_MG_REG_MCTP_TX_IF_EN_0_OFFSET           0

#define HIPCIEC_AP_MG_REG_MCTP_RX_RESET_1_LEN              1
#define HIPCIEC_AP_MG_REG_MCTP_RX_RESET_1_OFFSET           28
#define HIPCIEC_AP_MG_REG_MCTP_TX_RESET_1_LEN              1
#define HIPCIEC_AP_MG_REG_MCTP_TX_RESET_1_OFFSET           27
#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_EN_1_LEN            2
#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_EN_1_OFFSET         25
#define HIPCIEC_AP_MG_REG_MCTP_RSVD_PORT_NUM_1_LEN         5
#define HIPCIEC_AP_MG_REG_MCTP_RSVD_PORT_NUM_1_OFFSET      20
#define HIPCIEC_AP_MG_REG_MCTP_SUBSTITUTE_DROP_EN_1_LEN    2
#define HIPCIEC_AP_MG_REG_MCTP_SUBSTITUTE_DROP_EN_1_OFFSET 18
#define HIPCIEC_AP_MG_REG_MAX_PAYLOAD_SIZE_1_LEN           10
#define HIPCIEC_AP_MG_REG_MAX_PAYLOAD_SIZE_1_OFFSET        8
#define HIPCIEC_AP_MG_REG_MCTP_CFG_QUEUE_UNIT_1_LEN        3
#define HIPCIEC_AP_MG_REG_MCTP_CFG_QUEUE_UNIT_1_OFFSET     5
#define HIPCIEC_AP_MG_REG_MCTP_CFG_CHECK_EN_1_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_CFG_CHECK_EN_1_OFFSET       4
#define HIPCIEC_AP_MG_REG_MCTP_RX_EN_1_LEN                 1
#define HIPCIEC_AP_MG_REG_MCTP_RX_EN_1_OFFSET              3
#define HIPCIEC_AP_MG_REG_MCTP_RX_IF_EN_1_LEN              1
#define HIPCIEC_AP_MG_REG_MCTP_RX_IF_EN_1_OFFSET           2
#define HIPCIEC_AP_MG_REG_MCTP_TX_EN_1_LEN                 1
#define HIPCIEC_AP_MG_REG_MCTP_TX_EN_1_OFFSET              1
#define HIPCIEC_AP_MG_REG_MCTP_TX_IF_EN_1_LEN              1
#define HIPCIEC_AP_MG_REG_MCTP_TX_IF_EN_1_OFFSET           0

#define HIPCIEC_AP_MG_REG_MCTP_RX_RESET_2_LEN              1
#define HIPCIEC_AP_MG_REG_MCTP_RX_RESET_2_OFFSET           28
#define HIPCIEC_AP_MG_REG_MCTP_TX_RESET_2_LEN              1
#define HIPCIEC_AP_MG_REG_MCTP_TX_RESET_2_OFFSET           27
#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_EN_2_LEN            2
#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_EN_2_OFFSET         25
#define HIPCIEC_AP_MG_REG_MCTP_RSVD_PORT_NUM_2_LEN         5
#define HIPCIEC_AP_MG_REG_MCTP_RSVD_PORT_NUM_2_OFFSET      20
#define HIPCIEC_AP_MG_REG_MCTP_SUBSTITUTE_DROP_EN_2_LEN    2
#define HIPCIEC_AP_MG_REG_MCTP_SUBSTITUTE_DROP_EN_2_OFFSET 18
#define HIPCIEC_AP_MG_REG_MAX_PAYLOAD_SIZE_2_LEN           10
#define HIPCIEC_AP_MG_REG_MAX_PAYLOAD_SIZE_2_OFFSET        8
#define HIPCIEC_AP_MG_REG_MCTP_CFG_QUEUE_UNIT_2_LEN        3
#define HIPCIEC_AP_MG_REG_MCTP_CFG_QUEUE_UNIT_2_OFFSET     5
#define HIPCIEC_AP_MG_REG_MCTP_CFG_CHECK_EN_2_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_CFG_CHECK_EN_2_OFFSET       4
#define HIPCIEC_AP_MG_REG_MCTP_RX_EN_2_LEN                 1
#define HIPCIEC_AP_MG_REG_MCTP_RX_EN_2_OFFSET              3
#define HIPCIEC_AP_MG_REG_MCTP_RX_IF_EN_2_LEN              1
#define HIPCIEC_AP_MG_REG_MCTP_RX_IF_EN_2_OFFSET           2
#define HIPCIEC_AP_MG_REG_MCTP_TX_EN_2_LEN                 1
#define HIPCIEC_AP_MG_REG_MCTP_TX_EN_2_OFFSET              1
#define HIPCIEC_AP_MG_REG_MCTP_TX_IF_EN_2_LEN              1
#define HIPCIEC_AP_MG_REG_MCTP_TX_IF_EN_2_OFFSET           0

#define HIPCIEC_AP_MG_REG_MCTP_RSV0_0_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RSV0_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RSV0_1_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RSV0_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RSV0_2_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RSV0_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RSV1_0_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RSV1_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RSV1_1_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RSV1_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RSV1_2_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RSV1_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RSV2_0_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RSV2_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RSV2_1_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RSV2_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RSV2_2_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RSV2_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_ERR_MAPPING_0_LEN                  2
#define HIPCIEC_AP_MG_REG_ERR_MAPPING_0_OFFSET               14
#define HIPCIEC_AP_MG_REG_RX_OTHER_MSG_DROP_MAPPING_0_LEN    2
#define HIPCIEC_AP_MG_REG_RX_OTHER_MSG_DROP_MAPPING_0_OFFSET 12
#define HIPCIEC_AP_MG_REG_RX_PRI_MSG_DROP_MAPPING_0_LEN      2
#define HIPCIEC_AP_MG_REG_RX_PRI_MSG_DROP_MAPPING_0_OFFSET   10
#define HIPCIEC_AP_MG_REG_RX_MCTP_MSG_DROP_MAPPING_0_LEN     2
#define HIPCIEC_AP_MG_REG_RX_MCTP_MSG_DROP_MAPPING_0_OFFSET  8
#define HIPCIEC_AP_MG_REG_TX_MSG_CPL_MAPPING_0_LEN           2
#define HIPCIEC_AP_MG_REG_TX_MSG_CPL_MAPPING_0_OFFSET        6
#define HIPCIEC_AP_MG_REG_RX_OTHER_MSG_CPL_MAPPING_0_LEN     2
#define HIPCIEC_AP_MG_REG_RX_OTHER_MSG_CPL_MAPPING_0_OFFSET  4
#define HIPCIEC_AP_MG_REG_RX_PRI_MSG_CPL_MAPPING_0_LEN       2
#define HIPCIEC_AP_MG_REG_RX_PRI_MSG_CPL_MAPPING_0_OFFSET    2
#define HIPCIEC_AP_MG_REG_RX_MCTP_MSG_CPL_MAPPING_0_LEN      2
#define HIPCIEC_AP_MG_REG_RX_MCTP_MSG_CPL_MAPPING_0_OFFSET   0

#define HIPCIEC_AP_MG_REG_ERR_MAPPING_1_LEN                  2
#define HIPCIEC_AP_MG_REG_ERR_MAPPING_1_OFFSET               14
#define HIPCIEC_AP_MG_REG_RX_OTHER_MSG_DROP_MAPPING_1_LEN    2
#define HIPCIEC_AP_MG_REG_RX_OTHER_MSG_DROP_MAPPING_1_OFFSET 12
#define HIPCIEC_AP_MG_REG_RX_PRI_MSG_DROP_MAPPING_1_LEN      2
#define HIPCIEC_AP_MG_REG_RX_PRI_MSG_DROP_MAPPING_1_OFFSET   10
#define HIPCIEC_AP_MG_REG_RX_MCTP_MSG_DROP_MAPPING_1_LEN     2
#define HIPCIEC_AP_MG_REG_RX_MCTP_MSG_DROP_MAPPING_1_OFFSET  8
#define HIPCIEC_AP_MG_REG_TX_MSG_CPL_MAPPING_1_LEN           2
#define HIPCIEC_AP_MG_REG_TX_MSG_CPL_MAPPING_1_OFFSET        6
#define HIPCIEC_AP_MG_REG_RX_OTHER_MSG_CPL_MAPPING_1_LEN     2
#define HIPCIEC_AP_MG_REG_RX_OTHER_MSG_CPL_MAPPING_1_OFFSET  4
#define HIPCIEC_AP_MG_REG_RX_PRI_MSG_CPL_MAPPING_1_LEN       2
#define HIPCIEC_AP_MG_REG_RX_PRI_MSG_CPL_MAPPING_1_OFFSET    2
#define HIPCIEC_AP_MG_REG_RX_MCTP_MSG_CPL_MAPPING_1_LEN      2
#define HIPCIEC_AP_MG_REG_RX_MCTP_MSG_CPL_MAPPING_1_OFFSET   0

#define HIPCIEC_AP_MG_REG_ERR_MAPPING_2_LEN                  2
#define HIPCIEC_AP_MG_REG_ERR_MAPPING_2_OFFSET               14
#define HIPCIEC_AP_MG_REG_RX_OTHER_MSG_DROP_MAPPING_2_LEN    2
#define HIPCIEC_AP_MG_REG_RX_OTHER_MSG_DROP_MAPPING_2_OFFSET 12
#define HIPCIEC_AP_MG_REG_RX_PRI_MSG_DROP_MAPPING_2_LEN      2
#define HIPCIEC_AP_MG_REG_RX_PRI_MSG_DROP_MAPPING_2_OFFSET   10
#define HIPCIEC_AP_MG_REG_RX_MCTP_MSG_DROP_MAPPING_2_LEN     2
#define HIPCIEC_AP_MG_REG_RX_MCTP_MSG_DROP_MAPPING_2_OFFSET  8
#define HIPCIEC_AP_MG_REG_TX_MSG_CPL_MAPPING_2_LEN           2
#define HIPCIEC_AP_MG_REG_TX_MSG_CPL_MAPPING_2_OFFSET        6
#define HIPCIEC_AP_MG_REG_RX_OTHER_MSG_CPL_MAPPING_2_LEN     2
#define HIPCIEC_AP_MG_REG_RX_OTHER_MSG_CPL_MAPPING_2_OFFSET  4
#define HIPCIEC_AP_MG_REG_RX_PRI_MSG_CPL_MAPPING_2_LEN       2
#define HIPCIEC_AP_MG_REG_RX_PRI_MSG_CPL_MAPPING_2_OFFSET    2
#define HIPCIEC_AP_MG_REG_RX_MCTP_MSG_CPL_MAPPING_2_LEN      2
#define HIPCIEC_AP_MG_REG_RX_MCTP_MSG_CPL_MAPPING_2_OFFSET   0

#define HIPCIEC_AP_MG_REG_MCTP_RX_2BIT_ECC_ERR_INT_MSK_0_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_RX_2BIT_ECC_ERR_INT_MSK_0_OFFSET       14
#define HIPCIEC_AP_MG_REG_MCTP_TX_2BIT_ECC_ERR_INT_MSK_0_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_TX_2BIT_ECC_ERR_INT_MSK_0_OFFSET       13
#define HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_INT_MSK_0_LEN               1
#define HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_INT_MSK_0_OFFSET            12
#define HIPCIEC_AP_MG_REG_MCTP_TX_AXI_ERR_INT_MSK_0_LEN               1
#define HIPCIEC_AP_MG_REG_MCTP_TX_AXI_ERR_INT_MSK_0_OFFSET            11
#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_DROP_INT_MSK_0_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_DROP_INT_MSK_0_OFFSET     10
#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_DROP_INT_MSK_0_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_DROP_INT_MSK_0_OFFSET 9
#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_DROP_INT_MSK_0_LEN         1
#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_DROP_INT_MSK_0_OFFSET      8
#define HIPCIEC_AP_MG_REG_MCTP_TX_MSG_DROP_INT_MSK_0_LEN              1
#define HIPCIEC_AP_MG_REG_MCTP_TX_MSG_DROP_INT_MSK_0_OFFSET           7
#define HIPCIEC_AP_MG_REG_MCTP_RX_CHECK_FAIL_INT_MSK_0_LEN            1
#define HIPCIEC_AP_MG_REG_MCTP_RX_CHECK_FAIL_INT_MSK_0_OFFSET         6
#define HIPCIEC_AP_MG_REG_MCTP_TX_CHECK_FAIL_INT_MSK_0_LEN            1
#define HIPCIEC_AP_MG_REG_MCTP_TX_CHECK_FAIL_INT_MSK_0_OFFSET         5
#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_PEMPTY_INT_MSK_0_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_PEMPTY_INT_MSK_0_OFFSET       4
#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_CPL_INT_MSK_0_LEN         1
#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_CPL_INT_MSK_0_OFFSET      3
#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_CPL_INT_MSK_0_LEN     1
#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_CPL_INT_MSK_0_OFFSET  2
#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_CPL_INT_MSK_0_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_CPL_INT_MSK_0_OFFSET       1
#define HIPCIEC_AP_MG_REG_MCTP_TX_MSG_CPL_INT_MSK_0_LEN               1
#define HIPCIEC_AP_MG_REG_MCTP_TX_MSG_CPL_INT_MSK_0_OFFSET            0

#define HIPCIEC_AP_MG_REG_MCTP_RX_2BIT_ECC_ERR_INT_MSK_1_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_RX_2BIT_ECC_ERR_INT_MSK_1_OFFSET       14
#define HIPCIEC_AP_MG_REG_MCTP_TX_2BIT_ECC_ERR_INT_MSK_1_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_TX_2BIT_ECC_ERR_INT_MSK_1_OFFSET       13
#define HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_INT_MSK_1_LEN               1
#define HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_INT_MSK_1_OFFSET            12
#define HIPCIEC_AP_MG_REG_MCTP_TX_AXI_ERR_INT_MSK_1_LEN               1
#define HIPCIEC_AP_MG_REG_MCTP_TX_AXI_ERR_INT_MSK_1_OFFSET            11
#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_DROP_INT_MSK_1_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_DROP_INT_MSK_1_OFFSET     10
#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_DROP_INT_MSK_1_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_DROP_INT_MSK_1_OFFSET 9
#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_DROP_INT_MSK_1_LEN         1
#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_DROP_INT_MSK_1_OFFSET      8
#define HIPCIEC_AP_MG_REG_MCTP_TX_MSG_DROP_INT_MSK_1_LEN              1
#define HIPCIEC_AP_MG_REG_MCTP_TX_MSG_DROP_INT_MSK_1_OFFSET           7
#define HIPCIEC_AP_MG_REG_MCTP_RX_CHECK_FAIL_INT_MSK_1_LEN            1
#define HIPCIEC_AP_MG_REG_MCTP_RX_CHECK_FAIL_INT_MSK_1_OFFSET         6
#define HIPCIEC_AP_MG_REG_MCTP_TX_CHECK_FAIL_INT_MSK_1_LEN            1
#define HIPCIEC_AP_MG_REG_MCTP_TX_CHECK_FAIL_INT_MSK_1_OFFSET         5
#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_PEMPTY_INT_MSK_1_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_PEMPTY_INT_MSK_1_OFFSET       4
#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_CPL_INT_MSK_1_LEN         1
#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_CPL_INT_MSK_1_OFFSET      3
#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_CPL_INT_MSK_1_LEN     1
#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_CPL_INT_MSK_1_OFFSET  2
#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_CPL_INT_MSK_1_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_CPL_INT_MSK_1_OFFSET       1
#define HIPCIEC_AP_MG_REG_MCTP_TX_MSG_CPL_INT_MSK_1_LEN               1
#define HIPCIEC_AP_MG_REG_MCTP_TX_MSG_CPL_INT_MSK_1_OFFSET            0

#define HIPCIEC_AP_MG_REG_MCTP_RX_2BIT_ECC_ERR_INT_MSK_2_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_RX_2BIT_ECC_ERR_INT_MSK_2_OFFSET       14
#define HIPCIEC_AP_MG_REG_MCTP_TX_2BIT_ECC_ERR_INT_MSK_2_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_TX_2BIT_ECC_ERR_INT_MSK_2_OFFSET       13
#define HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_INT_MSK_2_LEN               1
#define HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_INT_MSK_2_OFFSET            12
#define HIPCIEC_AP_MG_REG_MCTP_TX_AXI_ERR_INT_MSK_2_LEN               1
#define HIPCIEC_AP_MG_REG_MCTP_TX_AXI_ERR_INT_MSK_2_OFFSET            11
#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_DROP_INT_MSK_2_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_DROP_INT_MSK_2_OFFSET     10
#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_DROP_INT_MSK_2_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_DROP_INT_MSK_2_OFFSET 9
#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_DROP_INT_MSK_2_LEN         1
#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_DROP_INT_MSK_2_OFFSET      8
#define HIPCIEC_AP_MG_REG_MCTP_TX_MSG_DROP_INT_MSK_2_LEN              1
#define HIPCIEC_AP_MG_REG_MCTP_TX_MSG_DROP_INT_MSK_2_OFFSET           7
#define HIPCIEC_AP_MG_REG_MCTP_RX_CHECK_FAIL_INT_MSK_2_LEN            1
#define HIPCIEC_AP_MG_REG_MCTP_RX_CHECK_FAIL_INT_MSK_2_OFFSET         6
#define HIPCIEC_AP_MG_REG_MCTP_TX_CHECK_FAIL_INT_MSK_2_LEN            1
#define HIPCIEC_AP_MG_REG_MCTP_TX_CHECK_FAIL_INT_MSK_2_OFFSET         5
#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_PEMPTY_INT_MSK_2_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_PEMPTY_INT_MSK_2_OFFSET       4
#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_CPL_INT_MSK_2_LEN         1
#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_CPL_INT_MSK_2_OFFSET      3
#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_CPL_INT_MSK_2_LEN     1
#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_CPL_INT_MSK_2_OFFSET  2
#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_CPL_INT_MSK_2_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_CPL_INT_MSK_2_OFFSET       1
#define HIPCIEC_AP_MG_REG_MCTP_TX_MSG_CPL_INT_MSK_2_LEN               1
#define HIPCIEC_AP_MG_REG_MCTP_TX_MSG_CPL_INT_MSK_2_OFFSET            0

#define HIPCIEC_AP_MG_REG_MCTP_RX_2BIT_ECC_ERR_INT_STS_0_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_RX_2BIT_ECC_ERR_INT_STS_0_OFFSET       14
#define HIPCIEC_AP_MG_REG_MCTP_TX_2BIT_ECC_ERR_INT_STS_0_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_TX_2BIT_ECC_ERR_INT_STS_0_OFFSET       13
#define HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_INT_STS_0_LEN               1
#define HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_INT_STS_0_OFFSET            12
#define HIPCIEC_AP_MG_REG_MCTP_TX_AXI_ERR_INT_STS_0_LEN               1
#define HIPCIEC_AP_MG_REG_MCTP_TX_AXI_ERR_INT_STS_0_OFFSET            11
#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_DROP_INT_STS_0_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_DROP_INT_STS_0_OFFSET     10
#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_DROP_INT_STS_0_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_DROP_INT_STS_0_OFFSET 9
#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_DROP_INT_STS_0_LEN         1
#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_DROP_INT_STS_0_OFFSET      8
#define HIPCIEC_AP_MG_REG_MCTP_TX_MSG_DROP_INT_STS_0_LEN              1
#define HIPCIEC_AP_MG_REG_MCTP_TX_MSG_DROP_INT_STS_0_OFFSET           7
#define HIPCIEC_AP_MG_REG_MCTP_RX_CHECK_FAIL_INT_STS_0_LEN            1
#define HIPCIEC_AP_MG_REG_MCTP_RX_CHECK_FAIL_INT_STS_0_OFFSET         6
#define HIPCIEC_AP_MG_REG_MCTP_TX_CHECK_FAIL_INT_STS_0_LEN            1
#define HIPCIEC_AP_MG_REG_MCTP_TX_CHECK_FAIL_INT_STS_0_OFFSET         5
#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_PEMPTY_INT_STS_0_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_PEMPTY_INT_STS_0_OFFSET       4
#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_CPL_INT_STS_0_LEN         1
#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_CPL_INT_STS_0_OFFSET      3
#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_CPL_INT_STS_0_LEN     1
#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_CPL_INT_STS_0_OFFSET  2
#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_CPL_INT_STS_0_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_CPL_INT_STS_0_OFFSET       1
#define HIPCIEC_AP_MG_REG_MCTP_TX_MSG_CPL_INT_STS_0_LEN               1
#define HIPCIEC_AP_MG_REG_MCTP_TX_MSG_CPL_INT_STS_0_OFFSET            0

#define HIPCIEC_AP_MG_REG_MCTP_RX_2BIT_ECC_ERR_INT_STS_1_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_RX_2BIT_ECC_ERR_INT_STS_1_OFFSET       14
#define HIPCIEC_AP_MG_REG_MCTP_TX_2BIT_ECC_ERR_INT_STS_1_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_TX_2BIT_ECC_ERR_INT_STS_1_OFFSET       13
#define HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_INT_STS_1_LEN               1
#define HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_INT_STS_1_OFFSET            12
#define HIPCIEC_AP_MG_REG_MCTP_TX_AXI_ERR_INT_STS_1_LEN               1
#define HIPCIEC_AP_MG_REG_MCTP_TX_AXI_ERR_INT_STS_1_OFFSET            11
#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_DROP_INT_STS_1_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_DROP_INT_STS_1_OFFSET     10
#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_DROP_INT_STS_1_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_DROP_INT_STS_1_OFFSET 9
#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_DROP_INT_STS_1_LEN         1
#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_DROP_INT_STS_1_OFFSET      8
#define HIPCIEC_AP_MG_REG_MCTP_TX_MSG_DROP_INT_STS_1_LEN              1
#define HIPCIEC_AP_MG_REG_MCTP_TX_MSG_DROP_INT_STS_1_OFFSET           7
#define HIPCIEC_AP_MG_REG_MCTP_RX_CHECK_FAIL_INT_STS_1_LEN            1
#define HIPCIEC_AP_MG_REG_MCTP_RX_CHECK_FAIL_INT_STS_1_OFFSET         6
#define HIPCIEC_AP_MG_REG_MCTP_TX_CHECK_FAIL_INT_STS_1_LEN            1
#define HIPCIEC_AP_MG_REG_MCTP_TX_CHECK_FAIL_INT_STS_1_OFFSET         5
#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_PEMPTY_INT_STS_1_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_PEMPTY_INT_STS_1_OFFSET       4
#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_CPL_INT_STS_1_LEN         1
#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_CPL_INT_STS_1_OFFSET      3
#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_CPL_INT_STS_1_LEN     1
#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_CPL_INT_STS_1_OFFSET  2
#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_CPL_INT_STS_1_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_CPL_INT_STS_1_OFFSET       1
#define HIPCIEC_AP_MG_REG_MCTP_TX_MSG_CPL_INT_STS_1_LEN               1
#define HIPCIEC_AP_MG_REG_MCTP_TX_MSG_CPL_INT_STS_1_OFFSET            0

#define HIPCIEC_AP_MG_REG_MCTP_RX_2BIT_ECC_ERR_INT_STS_2_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_RX_2BIT_ECC_ERR_INT_STS_2_OFFSET       14
#define HIPCIEC_AP_MG_REG_MCTP_TX_2BIT_ECC_ERR_INT_STS_2_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_TX_2BIT_ECC_ERR_INT_STS_2_OFFSET       13
#define HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_INT_STS_2_LEN               1
#define HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_INT_STS_2_OFFSET            12
#define HIPCIEC_AP_MG_REG_MCTP_TX_AXI_ERR_INT_STS_2_LEN               1
#define HIPCIEC_AP_MG_REG_MCTP_TX_AXI_ERR_INT_STS_2_OFFSET            11
#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_DROP_INT_STS_2_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_DROP_INT_STS_2_OFFSET     10
#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_DROP_INT_STS_2_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_DROP_INT_STS_2_OFFSET 9
#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_DROP_INT_STS_2_LEN         1
#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_DROP_INT_STS_2_OFFSET      8
#define HIPCIEC_AP_MG_REG_MCTP_TX_MSG_DROP_INT_STS_2_LEN              1
#define HIPCIEC_AP_MG_REG_MCTP_TX_MSG_DROP_INT_STS_2_OFFSET           7
#define HIPCIEC_AP_MG_REG_MCTP_RX_CHECK_FAIL_INT_STS_2_LEN            1
#define HIPCIEC_AP_MG_REG_MCTP_RX_CHECK_FAIL_INT_STS_2_OFFSET         6
#define HIPCIEC_AP_MG_REG_MCTP_TX_CHECK_FAIL_INT_STS_2_LEN            1
#define HIPCIEC_AP_MG_REG_MCTP_TX_CHECK_FAIL_INT_STS_2_OFFSET         5
#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_PEMPTY_INT_STS_2_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_PEMPTY_INT_STS_2_OFFSET       4
#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_CPL_INT_STS_2_LEN         1
#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_CPL_INT_STS_2_OFFSET      3
#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_CPL_INT_STS_2_LEN     1
#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_CPL_INT_STS_2_OFFSET  2
#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_CPL_INT_STS_2_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_CPL_INT_STS_2_OFFSET       1
#define HIPCIEC_AP_MG_REG_MCTP_TX_MSG_CPL_INT_STS_2_LEN               1
#define HIPCIEC_AP_MG_REG_MCTP_TX_MSG_CPL_INT_STS_2_OFFSET            0

#define HIPCIEC_AP_MG_REG_MCTP_RX_TIMEOUT_CFG_0_LEN    24
#define HIPCIEC_AP_MG_REG_MCTP_RX_TIMEOUT_CFG_0_OFFSET 8
#define HIPCIEC_AP_MG_REG_MCTP_RX_MULTI_TH_0_LEN       8
#define HIPCIEC_AP_MG_REG_MCTP_RX_MULTI_TH_0_OFFSET    0

#define HIPCIEC_AP_MG_REG_MCTP_RX_TIMEOUT_CFG_1_LEN    24
#define HIPCIEC_AP_MG_REG_MCTP_RX_TIMEOUT_CFG_1_OFFSET 8
#define HIPCIEC_AP_MG_REG_MCTP_RX_MULTI_TH_1_LEN       8
#define HIPCIEC_AP_MG_REG_MCTP_RX_MULTI_TH_1_OFFSET    0

#define HIPCIEC_AP_MG_REG_MCTP_RX_TIMEOUT_CFG_2_LEN    24
#define HIPCIEC_AP_MG_REG_MCTP_RX_TIMEOUT_CFG_2_OFFSET 8
#define HIPCIEC_AP_MG_REG_MCTP_RX_MULTI_TH_2_LEN       8
#define HIPCIEC_AP_MG_REG_MCTP_RX_MULTI_TH_2_OFFSET    0

#define HIPCIEC_AP_MG_REG_MCTP_RX_PEMPTY_THRESHOLD_0_LEN    8
#define HIPCIEC_AP_MG_REG_MCTP_RX_PEMPTY_THRESHOLD_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_PEMPTY_THRESHOLD_1_LEN    8
#define HIPCIEC_AP_MG_REG_MCTP_RX_PEMPTY_THRESHOLD_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_PEMPTY_THRESHOLD_2_LEN    8
#define HIPCIEC_AP_MG_REG_MCTP_RX_PEMPTY_THRESHOLD_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_HIGH_0_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_HIGH_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_HIGH_1_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_HIGH_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_HIGH_2_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_HIGH_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_LOW_0_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_LOW_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_LOW_1_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_LOW_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_LOW_2_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_LOW_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_DEPTH_0_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_DEPTH_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_DEPTH_1_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_DEPTH_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_DEPTH_2_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_DEPTH_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_HEAD_0_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_HEAD_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_HEAD_1_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_HEAD_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_HEAD_2_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_HEAD_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_TAIL_0_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_TAIL_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_TAIL_1_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_TAIL_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_TAIL_2_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_TAIL_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_HIGH_0_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_HIGH_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_HIGH_1_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_HIGH_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_HIGH_2_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_HIGH_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_LOW_0_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_LOW_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_LOW_1_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_LOW_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_LOW_2_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_LOW_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_DEPTH_0_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_DEPTH_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_DEPTH_1_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_DEPTH_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_DEPTH_2_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_DEPTH_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_HEAD_0_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_HEAD_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_HEAD_1_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_HEAD_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_HEAD_2_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_HEAD_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_TAIL_0_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_TAIL_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_TAIL_1_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_TAIL_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_TAIL_2_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_TAIL_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_HIGH_0_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_HIGH_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_HIGH_1_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_HIGH_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_HIGH_2_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_HIGH_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_LOW_0_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_LOW_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_LOW_1_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_LOW_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_LOW_2_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_LOW_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_HDR_FMT_FIELD_0_LEN       3
#define HIPCIEC_AP_MG_REG_MCTP_HDR_FMT_FIELD_0_OFFSET    29
#define HIPCIEC_AP_MG_REG_MCTP_HDR_TYPE_FIELD_0_LEN      5
#define HIPCIEC_AP_MG_REG_MCTP_HDR_TYPE_FIELD_0_OFFSET   24
#define HIPCIEC_AP_MG_REG_MCTP_HDR_T9_FIELD_0_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_HDR_T9_FIELD_0_OFFSET     23
#define HIPCIEC_AP_MG_REG_MCTP_HDR_TC_FIELD_0_LEN        3
#define HIPCIEC_AP_MG_REG_MCTP_HDR_TC_FIELD_0_OFFSET     20
#define HIPCIEC_AP_MG_REG_MCTP_HDR_T8_FIELD_0_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_HDR_T8_FIELD_0_OFFSET     19
#define HIPCIEC_AP_MG_REG_MCTP_HDR_ATTR2_FIELD_0_LEN     1
#define HIPCIEC_AP_MG_REG_MCTP_HDR_ATTR2_FIELD_0_OFFSET  18
#define HIPCIEC_AP_MG_REG_MCTP_HDR_RSV_FIELD0_0_LEN      1
#define HIPCIEC_AP_MG_REG_MCTP_HDR_RSV_FIELD0_0_OFFSET   17
#define HIPCIEC_AP_MG_REG_MCTP_HDR_TH_FIELD_0_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_HDR_TH_FIELD_0_OFFSET     16
#define HIPCIEC_AP_MG_REG_MCTP_HDR_TD_FIELD_0_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_HDR_TD_FIELD_0_OFFSET     15
#define HIPCIEC_AP_MG_REG_MCTP_HDR_EP_FIELD_0_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_HDR_EP_FIELD_0_OFFSET     14
#define HIPCIEC_AP_MG_REG_MCTP_HDR_ATTR10_FIELD_0_LEN    2
#define HIPCIEC_AP_MG_REG_MCTP_HDR_ATTR10_FIELD_0_OFFSET 12
#define HIPCIEC_AP_MG_REG_MCTP_HDR_AT_FIELD_0_LEN        2
#define HIPCIEC_AP_MG_REG_MCTP_HDR_AT_FIELD_0_OFFSET     10
#define HIPCIEC_AP_MG_REG_MCTP_HDR_LEN_FIELD_0_LEN       10
#define HIPCIEC_AP_MG_REG_MCTP_HDR_LEN_FIELD_0_OFFSET    0

#define HIPCIEC_AP_MG_REG_MCTP_HDR_FMT_FIELD_1_LEN       3
#define HIPCIEC_AP_MG_REG_MCTP_HDR_FMT_FIELD_1_OFFSET    29
#define HIPCIEC_AP_MG_REG_MCTP_HDR_TYPE_FIELD_1_LEN      5
#define HIPCIEC_AP_MG_REG_MCTP_HDR_TYPE_FIELD_1_OFFSET   24
#define HIPCIEC_AP_MG_REG_MCTP_HDR_T9_FIELD_1_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_HDR_T9_FIELD_1_OFFSET     23
#define HIPCIEC_AP_MG_REG_MCTP_HDR_TC_FIELD_1_LEN        3
#define HIPCIEC_AP_MG_REG_MCTP_HDR_TC_FIELD_1_OFFSET     20
#define HIPCIEC_AP_MG_REG_MCTP_HDR_T8_FIELD_1_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_HDR_T8_FIELD_1_OFFSET     19
#define HIPCIEC_AP_MG_REG_MCTP_HDR_ATTR2_FIELD_1_LEN     1
#define HIPCIEC_AP_MG_REG_MCTP_HDR_ATTR2_FIELD_1_OFFSET  18
#define HIPCIEC_AP_MG_REG_MCTP_HDR_RSV_FIELD0_1_LEN      1
#define HIPCIEC_AP_MG_REG_MCTP_HDR_RSV_FIELD0_1_OFFSET   17
#define HIPCIEC_AP_MG_REG_MCTP_HDR_TH_FIELD_1_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_HDR_TH_FIELD_1_OFFSET     16
#define HIPCIEC_AP_MG_REG_MCTP_HDR_TD_FIELD_1_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_HDR_TD_FIELD_1_OFFSET     15
#define HIPCIEC_AP_MG_REG_MCTP_HDR_EP_FIELD_1_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_HDR_EP_FIELD_1_OFFSET     14
#define HIPCIEC_AP_MG_REG_MCTP_HDR_ATTR10_FIELD_1_LEN    2
#define HIPCIEC_AP_MG_REG_MCTP_HDR_ATTR10_FIELD_1_OFFSET 12
#define HIPCIEC_AP_MG_REG_MCTP_HDR_AT_FIELD_1_LEN        2
#define HIPCIEC_AP_MG_REG_MCTP_HDR_AT_FIELD_1_OFFSET     10
#define HIPCIEC_AP_MG_REG_MCTP_HDR_LEN_FIELD_1_LEN       10
#define HIPCIEC_AP_MG_REG_MCTP_HDR_LEN_FIELD_1_OFFSET    0

#define HIPCIEC_AP_MG_REG_MCTP_HDR_FMT_FIELD_2_LEN       3
#define HIPCIEC_AP_MG_REG_MCTP_HDR_FMT_FIELD_2_OFFSET    29
#define HIPCIEC_AP_MG_REG_MCTP_HDR_TYPE_FIELD_2_LEN      5
#define HIPCIEC_AP_MG_REG_MCTP_HDR_TYPE_FIELD_2_OFFSET   24
#define HIPCIEC_AP_MG_REG_MCTP_HDR_T9_FIELD_2_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_HDR_T9_FIELD_2_OFFSET     23
#define HIPCIEC_AP_MG_REG_MCTP_HDR_TC_FIELD_2_LEN        3
#define HIPCIEC_AP_MG_REG_MCTP_HDR_TC_FIELD_2_OFFSET     20
#define HIPCIEC_AP_MG_REG_MCTP_HDR_T8_FIELD_2_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_HDR_T8_FIELD_2_OFFSET     19
#define HIPCIEC_AP_MG_REG_MCTP_HDR_ATTR2_FIELD_2_LEN     1
#define HIPCIEC_AP_MG_REG_MCTP_HDR_ATTR2_FIELD_2_OFFSET  18
#define HIPCIEC_AP_MG_REG_MCTP_HDR_RSV_FIELD0_2_LEN      1
#define HIPCIEC_AP_MG_REG_MCTP_HDR_RSV_FIELD0_2_OFFSET   17
#define HIPCIEC_AP_MG_REG_MCTP_HDR_TH_FIELD_2_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_HDR_TH_FIELD_2_OFFSET     16
#define HIPCIEC_AP_MG_REG_MCTP_HDR_TD_FIELD_2_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_HDR_TD_FIELD_2_OFFSET     15
#define HIPCIEC_AP_MG_REG_MCTP_HDR_EP_FIELD_2_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_HDR_EP_FIELD_2_OFFSET     14
#define HIPCIEC_AP_MG_REG_MCTP_HDR_ATTR10_FIELD_2_LEN    2
#define HIPCIEC_AP_MG_REG_MCTP_HDR_ATTR10_FIELD_2_OFFSET 12
#define HIPCIEC_AP_MG_REG_MCTP_HDR_AT_FIELD_2_LEN        2
#define HIPCIEC_AP_MG_REG_MCTP_HDR_AT_FIELD_2_OFFSET     10
#define HIPCIEC_AP_MG_REG_MCTP_HDR_LEN_FIELD_2_LEN       10
#define HIPCIEC_AP_MG_REG_MCTP_HDR_LEN_FIELD_2_OFFSET    0

#define HIPCIEC_AP_MG_REG_MCTP_HDR_RID_FIELD_0_LEN       16
#define HIPCIEC_AP_MG_REG_MCTP_HDR_RID_FIELD_0_OFFSET    16
#define HIPCIEC_AP_MG_REG_MCTP_HDR_RSV_FIELD1_0_LEN      2
#define HIPCIEC_AP_MG_REG_MCTP_HDR_RSV_FIELD1_0_OFFSET   14
#define HIPCIEC_AP_MG_REG_MCTP_HDR_PADLEN_FIELD_0_LEN    2
#define HIPCIEC_AP_MG_REG_MCTP_HDR_PADLEN_FIELD_0_OFFSET 12
#define HIPCIEC_AP_MG_REG_MCTP_HDR_VDM_FIELD_0_LEN       4
#define HIPCIEC_AP_MG_REG_MCTP_HDR_VDM_FIELD_0_OFFSET    8
#define HIPCIEC_AP_MG_REG_MCTP_HDR_MC_FIELD_0_LEN        8
#define HIPCIEC_AP_MG_REG_MCTP_HDR_MC_FIELD_0_OFFSET     0

#define HIPCIEC_AP_MG_REG_MCTP_HDR_RID_FIELD_1_LEN       16
#define HIPCIEC_AP_MG_REG_MCTP_HDR_RID_FIELD_1_OFFSET    16
#define HIPCIEC_AP_MG_REG_MCTP_HDR_RSV_FIELD1_1_LEN      2
#define HIPCIEC_AP_MG_REG_MCTP_HDR_RSV_FIELD1_1_OFFSET   14
#define HIPCIEC_AP_MG_REG_MCTP_HDR_PADLEN_FIELD_1_LEN    2
#define HIPCIEC_AP_MG_REG_MCTP_HDR_PADLEN_FIELD_1_OFFSET 12
#define HIPCIEC_AP_MG_REG_MCTP_HDR_VDM_FIELD_1_LEN       4
#define HIPCIEC_AP_MG_REG_MCTP_HDR_VDM_FIELD_1_OFFSET    8
#define HIPCIEC_AP_MG_REG_MCTP_HDR_MC_FIELD_1_LEN        8
#define HIPCIEC_AP_MG_REG_MCTP_HDR_MC_FIELD_1_OFFSET     0

#define HIPCIEC_AP_MG_REG_MCTP_HDR_RID_FIELD_2_LEN       16
#define HIPCIEC_AP_MG_REG_MCTP_HDR_RID_FIELD_2_OFFSET    16
#define HIPCIEC_AP_MG_REG_MCTP_HDR_RSV_FIELD1_2_LEN      2
#define HIPCIEC_AP_MG_REG_MCTP_HDR_RSV_FIELD1_2_OFFSET   14
#define HIPCIEC_AP_MG_REG_MCTP_HDR_PADLEN_FIELD_2_LEN    2
#define HIPCIEC_AP_MG_REG_MCTP_HDR_PADLEN_FIELD_2_OFFSET 12
#define HIPCIEC_AP_MG_REG_MCTP_HDR_VDM_FIELD_2_LEN       4
#define HIPCIEC_AP_MG_REG_MCTP_HDR_VDM_FIELD_2_OFFSET    8
#define HIPCIEC_AP_MG_REG_MCTP_HDR_MC_FIELD_2_LEN        8
#define HIPCIEC_AP_MG_REG_MCTP_HDR_MC_FIELD_2_OFFSET     0

#define HIPCIEC_AP_MG_REG_MCTP_HDR_TID_FIELD_0_LEN     16
#define HIPCIEC_AP_MG_REG_MCTP_HDR_TID_FIELD_0_OFFSET  16
#define HIPCIEC_AP_MG_REG_MCTP_HDR_VDID_FIELD_0_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_HDR_VDID_FIELD_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_HDR_TID_FIELD_1_LEN     16
#define HIPCIEC_AP_MG_REG_MCTP_HDR_TID_FIELD_1_OFFSET  16
#define HIPCIEC_AP_MG_REG_MCTP_HDR_VDID_FIELD_1_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_HDR_VDID_FIELD_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_HDR_TID_FIELD_2_LEN     16
#define HIPCIEC_AP_MG_REG_MCTP_HDR_TID_FIELD_2_OFFSET  16
#define HIPCIEC_AP_MG_REG_MCTP_HDR_VDID_FIELD_2_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_HDR_VDID_FIELD_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_ERR_MSG_CNT_0_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_TX_ERR_MSG_CNT_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_ERR_MSG_CNT_1_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_TX_ERR_MSG_CNT_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_ERR_MSG_CNT_2_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_TX_ERR_MSG_CNT_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCPT_TX_ERR_MSG_AXI_0_LEN    16
#define HIPCIEC_AP_MG_REG_MCPT_TX_ERR_MSG_AXI_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCPT_TX_ERR_MSG_AXI_1_LEN    16
#define HIPCIEC_AP_MG_REG_MCPT_TX_ERR_MSG_AXI_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCPT_TX_ERR_MSG_AXI_2_LEN    16
#define HIPCIEC_AP_MG_REG_MCPT_TX_ERR_MSG_AXI_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_ERR_MSG_CHECK_0_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_RX_ERR_MSG_CHECK_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_ERR_MSG_CHECK_1_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_RX_ERR_MSG_CHECK_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_ERR_MSG_CHECK_2_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_RX_ERR_MSG_CHECK_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCPT_RX_ERR_MSG_TL_0_LEN    16
#define HIPCIEC_AP_MG_REG_MCPT_RX_ERR_MSG_TL_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCPT_RX_ERR_MSG_TL_1_LEN    16
#define HIPCIEC_AP_MG_REG_MCPT_RX_ERR_MSG_TL_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCPT_RX_ERR_MSG_TL_2_LEN    16
#define HIPCIEC_AP_MG_REG_MCPT_RX_ERR_MSG_TL_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_CTRL_FIFO_ERROR_0_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_TX_CTRL_FIFO_ERROR_0_OFFSET     27
#define HIPCIEC_AP_MG_REG_MCTP_TX_CTRL_FIFO_FULL_0_LEN         1
#define HIPCIEC_AP_MG_REG_MCTP_TX_CTRL_FIFO_FULL_0_OFFSET      26
#define HIPCIEC_AP_MG_REG_MCTP_TX_CTRL_FIFO_EMPTY_0_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_TX_CTRL_FIFO_EMPTY_0_OFFSET     25
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_PUSH_OVERFLOW_0_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_PUSH_OVERFLOW_0_OFFSET 24
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_POP_UNDERFLOW_0_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_POP_UNDERFLOW_0_OFFSET 23
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_FULL_0_LEN             1
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_FULL_0_OFFSET          22
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_PFULL_0_LEN            1
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_PFULL_0_OFFSET         21
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_EMPTY_0_LEN            1
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_EMPTY_0_OFFSET         20
#define HIPCIEC_AP_MG_REG_MCTP_RX_P_RESP_FIFO_ERROR_0_LEN      1
#define HIPCIEC_AP_MG_REG_MCTP_RX_P_RESP_FIFO_ERROR_0_OFFSET   19
#define HIPCIEC_AP_MG_REG_MCTP_RX_P_RESP_FIFO_FULL_0_LEN       1
#define HIPCIEC_AP_MG_REG_MCTP_RX_P_RESP_FIFO_FULL_0_OFFSET    18
#define HIPCIEC_AP_MG_REG_MCTP_RX_P_RESP_FIFO_EMPTY_0_LEN      1
#define HIPCIEC_AP_MG_REG_MCTP_RX_P_RESP_FIFO_EMPTY_0_OFFSET   17
#define HIPCIEC_AP_MG_REG_MCTP_RX_WR_FIFO_ERROR_0_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_RX_WR_FIFO_ERROR_0_OFFSET       16
#define HIPCIEC_AP_MG_REG_MCTP_RX_WR_FIFO_FULL_0_LEN           1
#define HIPCIEC_AP_MG_REG_MCTP_RX_WR_FIFO_FULL_0_OFFSET        15
#define HIPCIEC_AP_MG_REG_MCTP_RX_WR_FIFO_EMPTY_0_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_RX_WR_FIFO_EMPTY_0_OFFSET       14
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAG_FIFO_ERROR_0_LEN         1
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAG_FIFO_ERROR_0_OFFSET      13
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAG_FIFO_FULL_0_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAG_FIFO_FULL_0_OFFSET       12
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAG_FIFO_EMPTY_0_LEN         1
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAG_FIFO_EMPTY_0_OFFSET      11
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAIL_FIFO_ERROR_0_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAIL_FIFO_ERROR_0_OFFSET     10
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAIL_FIFO_FULL_0_LEN         1
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAIL_FIFO_FULL_0_OFFSET      9
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAIL_FIFO_EMPTY_0_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAIL_FIFO_EMPTY_0_OFFSET     8
#define HIPCIEC_AP_MG_REG_MCTP_RX_CTRL_FIFO_ERROR_0_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_RX_CTRL_FIFO_ERROR_0_OFFSET     7
#define HIPCIEC_AP_MG_REG_MCTP_RX_CTRL_FIFO_FULL_0_LEN         1
#define HIPCIEC_AP_MG_REG_MCTP_RX_CTRL_FIFO_FULL_0_OFFSET      6
#define HIPCIEC_AP_MG_REG_MCTP_RX_CTRL_FIFO_EMPTY_0_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_RX_CTRL_FIFO_EMPTY_0_OFFSET     5
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_PUSH_OVERFLOW_0_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_PUSH_OVERFLOW_0_OFFSET 4
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_POP_UNDERFLOW_0_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_POP_UNDERFLOW_0_OFFSET 3
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_FULL_0_LEN             1
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_FULL_0_OFFSET          2
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_PFULL_0_LEN            1
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_PFULL_0_OFFSET         1
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_EMPTY_0_LEN            1
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_EMPTY_0_OFFSET         0

#define HIPCIEC_AP_MG_REG_MCTP_TX_CTRL_FIFO_ERROR_1_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_TX_CTRL_FIFO_ERROR_1_OFFSET     27
#define HIPCIEC_AP_MG_REG_MCTP_TX_CTRL_FIFO_FULL_1_LEN         1
#define HIPCIEC_AP_MG_REG_MCTP_TX_CTRL_FIFO_FULL_1_OFFSET      26
#define HIPCIEC_AP_MG_REG_MCTP_TX_CTRL_FIFO_EMPTY_1_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_TX_CTRL_FIFO_EMPTY_1_OFFSET     25
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_PUSH_OVERFLOW_1_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_PUSH_OVERFLOW_1_OFFSET 24
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_POP_UNDERFLOW_1_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_POP_UNDERFLOW_1_OFFSET 23
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_FULL_1_LEN             1
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_FULL_1_OFFSET          22
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_PFULL_1_LEN            1
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_PFULL_1_OFFSET         21
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_EMPTY_1_LEN            1
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_EMPTY_1_OFFSET         20
#define HIPCIEC_AP_MG_REG_MCTP_RX_P_RESP_FIFO_ERROR_1_LEN      1
#define HIPCIEC_AP_MG_REG_MCTP_RX_P_RESP_FIFO_ERROR_1_OFFSET   19
#define HIPCIEC_AP_MG_REG_MCTP_RX_P_RESP_FIFO_FULL_1_LEN       1
#define HIPCIEC_AP_MG_REG_MCTP_RX_P_RESP_FIFO_FULL_1_OFFSET    18
#define HIPCIEC_AP_MG_REG_MCTP_RX_P_RESP_FIFO_EMPTY_1_LEN      1
#define HIPCIEC_AP_MG_REG_MCTP_RX_P_RESP_FIFO_EMPTY_1_OFFSET   17
#define HIPCIEC_AP_MG_REG_MCTP_RX_WR_FIFO_ERROR_1_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_RX_WR_FIFO_ERROR_1_OFFSET       16
#define HIPCIEC_AP_MG_REG_MCTP_RX_WR_FIFO_FULL_1_LEN           1
#define HIPCIEC_AP_MG_REG_MCTP_RX_WR_FIFO_FULL_1_OFFSET        15
#define HIPCIEC_AP_MG_REG_MCTP_RX_WR_FIFO_EMPTY_1_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_RX_WR_FIFO_EMPTY_1_OFFSET       14
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAG_FIFO_ERROR_1_LEN         1
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAG_FIFO_ERROR_1_OFFSET      13
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAG_FIFO_FULL_1_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAG_FIFO_FULL_1_OFFSET       12
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAG_FIFO_EMPTY_1_LEN         1
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAG_FIFO_EMPTY_1_OFFSET      11
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAIL_FIFO_ERROR_1_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAIL_FIFO_ERROR_1_OFFSET     10
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAIL_FIFO_FULL_1_LEN         1
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAIL_FIFO_FULL_1_OFFSET      9
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAIL_FIFO_EMPTY_1_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAIL_FIFO_EMPTY_1_OFFSET     8
#define HIPCIEC_AP_MG_REG_MCTP_RX_CTRL_FIFO_ERROR_1_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_RX_CTRL_FIFO_ERROR_1_OFFSET     7
#define HIPCIEC_AP_MG_REG_MCTP_RX_CTRL_FIFO_FULL_1_LEN         1
#define HIPCIEC_AP_MG_REG_MCTP_RX_CTRL_FIFO_FULL_1_OFFSET      6
#define HIPCIEC_AP_MG_REG_MCTP_RX_CTRL_FIFO_EMPTY_1_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_RX_CTRL_FIFO_EMPTY_1_OFFSET     5
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_PUSH_OVERFLOW_1_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_PUSH_OVERFLOW_1_OFFSET 4
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_POP_UNDERFLOW_1_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_POP_UNDERFLOW_1_OFFSET 3
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_FULL_1_LEN             1
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_FULL_1_OFFSET          2
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_PFULL_1_LEN            1
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_PFULL_1_OFFSET         1
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_EMPTY_1_LEN            1
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_EMPTY_1_OFFSET         0

#define HIPCIEC_AP_MG_REG_MCTP_TX_CTRL_FIFO_ERROR_2_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_TX_CTRL_FIFO_ERROR_2_OFFSET     27
#define HIPCIEC_AP_MG_REG_MCTP_TX_CTRL_FIFO_FULL_2_LEN         1
#define HIPCIEC_AP_MG_REG_MCTP_TX_CTRL_FIFO_FULL_2_OFFSET      26
#define HIPCIEC_AP_MG_REG_MCTP_TX_CTRL_FIFO_EMPTY_2_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_TX_CTRL_FIFO_EMPTY_2_OFFSET     25
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_PUSH_OVERFLOW_2_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_PUSH_OVERFLOW_2_OFFSET 24
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_POP_UNDERFLOW_2_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_POP_UNDERFLOW_2_OFFSET 23
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_FULL_2_LEN             1
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_FULL_2_OFFSET          22
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_PFULL_2_LEN            1
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_PFULL_2_OFFSET         21
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_EMPTY_2_LEN            1
#define HIPCIEC_AP_MG_REG_MCTP_TX_DFIFO_EMPTY_2_OFFSET         20
#define HIPCIEC_AP_MG_REG_MCTP_RX_P_RESP_FIFO_ERROR_2_LEN      1
#define HIPCIEC_AP_MG_REG_MCTP_RX_P_RESP_FIFO_ERROR_2_OFFSET   19
#define HIPCIEC_AP_MG_REG_MCTP_RX_P_RESP_FIFO_FULL_2_LEN       1
#define HIPCIEC_AP_MG_REG_MCTP_RX_P_RESP_FIFO_FULL_2_OFFSET    18
#define HIPCIEC_AP_MG_REG_MCTP_RX_P_RESP_FIFO_EMPTY_2_LEN      1
#define HIPCIEC_AP_MG_REG_MCTP_RX_P_RESP_FIFO_EMPTY_2_OFFSET   17
#define HIPCIEC_AP_MG_REG_MCTP_RX_WR_FIFO_ERROR_2_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_RX_WR_FIFO_ERROR_2_OFFSET       16
#define HIPCIEC_AP_MG_REG_MCTP_RX_WR_FIFO_FULL_2_LEN           1
#define HIPCIEC_AP_MG_REG_MCTP_RX_WR_FIFO_FULL_2_OFFSET        15
#define HIPCIEC_AP_MG_REG_MCTP_RX_WR_FIFO_EMPTY_2_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_RX_WR_FIFO_EMPTY_2_OFFSET       14
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAG_FIFO_ERROR_2_LEN         1
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAG_FIFO_ERROR_2_OFFSET      13
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAG_FIFO_FULL_2_LEN          1
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAG_FIFO_FULL_2_OFFSET       12
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAG_FIFO_EMPTY_2_LEN         1
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAG_FIFO_EMPTY_2_OFFSET      11
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAIL_FIFO_ERROR_2_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAIL_FIFO_ERROR_2_OFFSET     10
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAIL_FIFO_FULL_2_LEN         1
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAIL_FIFO_FULL_2_OFFSET      9
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAIL_FIFO_EMPTY_2_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_RX_TAIL_FIFO_EMPTY_2_OFFSET     8
#define HIPCIEC_AP_MG_REG_MCTP_RX_CTRL_FIFO_ERROR_2_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_RX_CTRL_FIFO_ERROR_2_OFFSET     7
#define HIPCIEC_AP_MG_REG_MCTP_RX_CTRL_FIFO_FULL_2_LEN         1
#define HIPCIEC_AP_MG_REG_MCTP_RX_CTRL_FIFO_FULL_2_OFFSET      6
#define HIPCIEC_AP_MG_REG_MCTP_RX_CTRL_FIFO_EMPTY_2_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_RX_CTRL_FIFO_EMPTY_2_OFFSET     5
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_PUSH_OVERFLOW_2_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_PUSH_OVERFLOW_2_OFFSET 4
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_POP_UNDERFLOW_2_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_POP_UNDERFLOW_2_OFFSET 3
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_FULL_2_LEN             1
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_FULL_2_OFFSET          2
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_PFULL_2_LEN            1
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_PFULL_2_OFFSET         1
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_EMPTY_2_LEN            1
#define HIPCIEC_AP_MG_REG_MCTP_RX_DFIFO_EMPTY_2_OFFSET         0

#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_TH_0_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_TH_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_TH_1_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_TH_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_TH_2_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_TH_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_FIFO_OVERFLOW_PKT_NUM_0_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_FIFO_OVERFLOW_PKT_NUM_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_FIFO_OVERFLOW_PKT_NUM_1_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_FIFO_OVERFLOW_PKT_NUM_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_FIFO_OVERFLOW_PKT_NUM_2_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_FIFO_OVERFLOW_PKT_NUM_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_MCTP_ROUTING_ERR_CNT_0_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_TX_MCTP_ROUTING_ERR_CNT_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_MCTP_ROUTING_ERR_CNT_1_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_TX_MCTP_ROUTING_ERR_CNT_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_MCTP_ROUTING_ERR_CNT_2_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_TX_MCTP_ROUTING_ERR_CNT_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_OTHER_ROUTING_ERR_CNT_0_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_TX_OTHER_ROUTING_ERR_CNT_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_OTHER_ROUTING_ERR_CNT_1_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_TX_OTHER_ROUTING_ERR_CNT_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_OTHER_ROUTING_ERR_CNT_2_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_TX_OTHER_ROUTING_ERR_CNT_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_MCTP_MSG_NUM_0_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_TX_MCTP_MSG_NUM_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_MCTP_MSG_NUM_1_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_TX_MCTP_MSG_NUM_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_MCTP_MSG_NUM_2_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_TX_MCTP_MSG_NUM_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_INVLD_PRI_MSG_NUM_0_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_TX_INVLD_PRI_MSG_NUM_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_INVLD_PRI_MSG_NUM_1_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_TX_INVLD_PRI_MSG_NUM_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_INVLD_PRI_MSG_NUM_2_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_TX_INVLD_PRI_MSG_NUM_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_OTHER_MSG_NUM_0_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_TX_OTHER_MSG_NUM_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_OTHER_MSG_NUM_1_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_TX_OTHER_MSG_NUM_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_OTHER_MSG_NUM_2_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_TX_OTHER_MSG_NUM_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_NUM_0_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_NUM_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_NUM_1_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_NUM_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_NUM_2_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_MCTP_MSG_NUM_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_NUM_0_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_NUM_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_NUM_1_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_NUM_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_NUM_2_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_INVLD_PRI_MSG_NUM_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_NUM_0_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_NUM_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_NUM_1_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_NUM_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_NUM_2_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_OTHER_MSG_NUM_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_OUTSTANDING_CNT_0_LEN    4
#define HIPCIEC_AP_MG_REG_MCTP_RX_OUTSTANDING_CNT_0_OFFSET 16
#define HIPCIEC_AP_MG_REG_MCTP_TX_OUTSTANDING_CNT_0_LEN    4
#define HIPCIEC_AP_MG_REG_MCTP_TX_OUTSTANDING_CNT_0_OFFSET 12
#define HIPCIEC_AP_MG_REG_MCTP_RX_FSM_STATE_0_LEN          5
#define HIPCIEC_AP_MG_REG_MCTP_RX_FSM_STATE_0_OFFSET       7
#define HIPCIEC_AP_MG_REG_MCTP_TX_FSM_STATE_0_LEN          7
#define HIPCIEC_AP_MG_REG_MCTP_TX_FSM_STATE_0_OFFSET       0

#define HIPCIEC_AP_MG_REG_MCTP_RX_OUTSTANDING_CNT_1_LEN    4
#define HIPCIEC_AP_MG_REG_MCTP_RX_OUTSTANDING_CNT_1_OFFSET 16
#define HIPCIEC_AP_MG_REG_MCTP_TX_OUTSTANDING_CNT_1_LEN    4
#define HIPCIEC_AP_MG_REG_MCTP_TX_OUTSTANDING_CNT_1_OFFSET 12
#define HIPCIEC_AP_MG_REG_MCTP_RX_FSM_STATE_1_LEN          5
#define HIPCIEC_AP_MG_REG_MCTP_RX_FSM_STATE_1_OFFSET       7
#define HIPCIEC_AP_MG_REG_MCTP_TX_FSM_STATE_1_LEN          7
#define HIPCIEC_AP_MG_REG_MCTP_TX_FSM_STATE_1_OFFSET       0

#define HIPCIEC_AP_MG_REG_MCTP_RX_OUTSTANDING_CNT_2_LEN    4
#define HIPCIEC_AP_MG_REG_MCTP_RX_OUTSTANDING_CNT_2_OFFSET 16
#define HIPCIEC_AP_MG_REG_MCTP_TX_OUTSTANDING_CNT_2_LEN    4
#define HIPCIEC_AP_MG_REG_MCTP_TX_OUTSTANDING_CNT_2_OFFSET 12
#define HIPCIEC_AP_MG_REG_MCTP_RX_FSM_STATE_2_LEN          5
#define HIPCIEC_AP_MG_REG_MCTP_RX_FSM_STATE_2_OFFSET       7
#define HIPCIEC_AP_MG_REG_MCTP_TX_FSM_STATE_2_LEN          7
#define HIPCIEC_AP_MG_REG_MCTP_TX_FSM_STATE_2_OFFSET       0

#define HIPCIEC_AP_MG_REG_MCTP_TX_LEN_UNMAT_0_LEN     1
#define HIPCIEC_AP_MG_REG_MCTP_TX_LEN_UNMAT_0_OFFSET  6
#define HIPCIEC_AP_MG_REG_MCTP_RX_LEN_UNMAT_0_LEN     1
#define HIPCIEC_AP_MG_REG_MCTP_RX_LEN_UNMAT_0_OFFSET  5
#define HIPCIEC_AP_MG_REG_MCTP_TX_FMT_UNMAT_0_LEN     1
#define HIPCIEC_AP_MG_REG_MCTP_TX_FMT_UNMAT_0_OFFSET  4
#define HIPCIEC_AP_MG_REG_MCTP_TX_TYPE_UNMAT_0_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_TX_TYPE_UNMAT_0_OFFSET 3
#define HIPCIEC_AP_MG_REG_MCTP_TX_VDM_UNMAT_0_LEN     1
#define HIPCIEC_AP_MG_REG_MCTP_TX_VDM_UNMAT_0_OFFSET  2
#define HIPCIEC_AP_MG_REG_MCTP_TX_MC_UNMAT_0_LEN      1
#define HIPCIEC_AP_MG_REG_MCTP_TX_MC_UNMAT_0_OFFSET   1
#define HIPCIEC_AP_MG_REG_MCTP_TX_VDID_UNMAT_0_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_TX_VDID_UNMAT_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_LEN_UNMAT_1_LEN     1
#define HIPCIEC_AP_MG_REG_MCTP_TX_LEN_UNMAT_1_OFFSET  6
#define HIPCIEC_AP_MG_REG_MCTP_RX_LEN_UNMAT_1_LEN     1
#define HIPCIEC_AP_MG_REG_MCTP_RX_LEN_UNMAT_1_OFFSET  5
#define HIPCIEC_AP_MG_REG_MCTP_TX_FMT_UNMAT_1_LEN     1
#define HIPCIEC_AP_MG_REG_MCTP_TX_FMT_UNMAT_1_OFFSET  4
#define HIPCIEC_AP_MG_REG_MCTP_TX_TYPE_UNMAT_1_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_TX_TYPE_UNMAT_1_OFFSET 3
#define HIPCIEC_AP_MG_REG_MCTP_TX_VDM_UNMAT_1_LEN     1
#define HIPCIEC_AP_MG_REG_MCTP_TX_VDM_UNMAT_1_OFFSET  2
#define HIPCIEC_AP_MG_REG_MCTP_TX_MC_UNMAT_1_LEN      1
#define HIPCIEC_AP_MG_REG_MCTP_TX_MC_UNMAT_1_OFFSET   1
#define HIPCIEC_AP_MG_REG_MCTP_TX_VDID_UNMAT_1_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_TX_VDID_UNMAT_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_LEN_UNMAT_2_LEN     1
#define HIPCIEC_AP_MG_REG_MCTP_TX_LEN_UNMAT_2_OFFSET  6
#define HIPCIEC_AP_MG_REG_MCTP_RX_LEN_UNMAT_2_LEN     1
#define HIPCIEC_AP_MG_REG_MCTP_RX_LEN_UNMAT_2_OFFSET  5
#define HIPCIEC_AP_MG_REG_MCTP_TX_FMT_UNMAT_2_LEN     1
#define HIPCIEC_AP_MG_REG_MCTP_TX_FMT_UNMAT_2_OFFSET  4
#define HIPCIEC_AP_MG_REG_MCTP_TX_TYPE_UNMAT_2_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_TX_TYPE_UNMAT_2_OFFSET 3
#define HIPCIEC_AP_MG_REG_MCTP_TX_VDM_UNMAT_2_LEN     1
#define HIPCIEC_AP_MG_REG_MCTP_TX_VDM_UNMAT_2_OFFSET  2
#define HIPCIEC_AP_MG_REG_MCTP_TX_MC_UNMAT_2_LEN      1
#define HIPCIEC_AP_MG_REG_MCTP_TX_MC_UNMAT_2_OFFSET   1
#define HIPCIEC_AP_MG_REG_MCTP_TX_VDID_UNMAT_2_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_TX_VDID_UNMAT_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_LPB_EN_0_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_LPB_EN_0_OFFSET     1
#define HIPCIEC_AP_MG_REG_MCTP_INF_DFX_EN_0_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_INF_DFX_EN_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_LPB_EN_1_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_LPB_EN_1_OFFSET     1
#define HIPCIEC_AP_MG_REG_MCTP_INF_DFX_EN_1_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_INF_DFX_EN_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_LPB_EN_2_LEN        1
#define HIPCIEC_AP_MG_REG_MCTP_LPB_EN_2_OFFSET     1
#define HIPCIEC_AP_MG_REG_MCTP_INF_DFX_EN_2_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_INF_DFX_EN_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_DATA_FIFO_ECC_1BIT_INJECT_0_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_RX_DATA_FIFO_ECC_1BIT_INJECT_0_OFFSET 3
#define HIPCIEC_AP_MG_REG_MCTP_RX_DATA_FIFO_ECC_2BIT_INJECT_0_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_RX_DATA_FIFO_ECC_2BIT_INJECT_0_OFFSET 2
#define HIPCIEC_AP_MG_REG_MCTP_TX_DATA_FIFO_ECC_1BIT_INJECT_0_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_TX_DATA_FIFO_ECC_1BIT_INJECT_0_OFFSET 1
#define HIPCIEC_AP_MG_REG_MCTP_TX_DATA_FIFO_ECC_2BIT_INJECT_0_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_TX_DATA_FIFO_ECC_2BIT_INJECT_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_DATA_FIFO_ECC_1BIT_INJECT_1_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_RX_DATA_FIFO_ECC_1BIT_INJECT_1_OFFSET 3
#define HIPCIEC_AP_MG_REG_MCTP_RX_DATA_FIFO_ECC_2BIT_INJECT_1_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_RX_DATA_FIFO_ECC_2BIT_INJECT_1_OFFSET 2
#define HIPCIEC_AP_MG_REG_MCTP_TX_DATA_FIFO_ECC_1BIT_INJECT_1_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_TX_DATA_FIFO_ECC_1BIT_INJECT_1_OFFSET 1
#define HIPCIEC_AP_MG_REG_MCTP_TX_DATA_FIFO_ECC_2BIT_INJECT_1_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_TX_DATA_FIFO_ECC_2BIT_INJECT_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_DATA_FIFO_ECC_1BIT_INJECT_2_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_RX_DATA_FIFO_ECC_1BIT_INJECT_2_OFFSET 3
#define HIPCIEC_AP_MG_REG_MCTP_RX_DATA_FIFO_ECC_2BIT_INJECT_2_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_RX_DATA_FIFO_ECC_2BIT_INJECT_2_OFFSET 2
#define HIPCIEC_AP_MG_REG_MCTP_TX_DATA_FIFO_ECC_1BIT_INJECT_2_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_TX_DATA_FIFO_ECC_1BIT_INJECT_2_OFFSET 1
#define HIPCIEC_AP_MG_REG_MCTP_TX_DATA_FIFO_ECC_2BIT_INJECT_2_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_TX_DATA_FIFO_ECC_2BIT_INJECT_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_ECC_1BIT_ERR_CNT_0_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_RX_ECC_1BIT_ERR_CNT_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_ECC_1BIT_ERR_CNT_1_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_RX_ECC_1BIT_ERR_CNT_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_ECC_1BIT_ERR_CNT_2_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_RX_ECC_1BIT_ERR_CNT_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_ECC_2BIT_ERR_CNT_0_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_RX_ECC_2BIT_ERR_CNT_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_ECC_2BIT_ERR_CNT_1_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_RX_ECC_2BIT_ERR_CNT_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_ECC_2BIT_ERR_CNT_2_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_RX_ECC_2BIT_ERR_CNT_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_ECC_1BIT_ERR_CNT_0_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_TX_ECC_1BIT_ERR_CNT_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_ECC_1BIT_ERR_CNT_1_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_TX_ECC_1BIT_ERR_CNT_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_ECC_1BIT_ERR_CNT_2_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_TX_ECC_1BIT_ERR_CNT_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_ECC_2BIT_ERR_CNT_0_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_TX_ECC_2BIT_ERR_CNT_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_ECC_2BIT_ERR_CNT_1_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_TX_ECC_2BIT_ERR_CNT_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_ECC_2BIT_ERR_CNT_2_LEN    16
#define HIPCIEC_AP_MG_REG_MCTP_TX_ECC_2BIT_ERR_CNT_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW0_0_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW0_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW0_1_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW0_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW0_2_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW0_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW1_0_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW1_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW1_1_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW1_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW1_2_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW1_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW2_0_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW2_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW2_1_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW2_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW2_2_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW2_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW3_0_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW3_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW3_1_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW3_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW3_2_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW3_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_ATTR_0_LEN    3
#define HIPCIEC_AP_MG_REG_MCTP_RX_ATTR_0_OFFSET 3
#define HIPCIEC_AP_MG_REG_MCTP_TX_ATTR_0_LEN    3
#define HIPCIEC_AP_MG_REG_MCTP_TX_ATTR_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_ATTR_1_LEN    3
#define HIPCIEC_AP_MG_REG_MCTP_RX_ATTR_1_OFFSET 3
#define HIPCIEC_AP_MG_REG_MCTP_TX_ATTR_1_LEN    3
#define HIPCIEC_AP_MG_REG_MCTP_TX_ATTR_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_ATTR_2_LEN    3
#define HIPCIEC_AP_MG_REG_MCTP_RX_ATTR_2_OFFSET 3
#define HIPCIEC_AP_MG_REG_MCTP_TX_ATTR_2_LEN    3
#define HIPCIEC_AP_MG_REG_MCTP_TX_ATTR_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_STRMID_0_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_STRMID_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_STRMID_1_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_STRMID_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_RX_STRMID_2_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_RX_STRMID_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_STRMID_0_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_TX_STRMID_0_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_STRMID_1_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_TX_STRMID_1_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_STRMID_2_LEN    32
#define HIPCIEC_AP_MG_REG_MCTP_TX_STRMID_2_OFFSET 0

#define HIPCIEC_AP_MG_REG_MCTP_TX_BROADCAST_FIFO_ERROR_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_TX_BROADCAST_FIFO_ERROR_OFFSET 18
#define HIPCIEC_AP_MG_REG_MCTP_TX_BROADCAST_FIFO_FULL_LEN     1
#define HIPCIEC_AP_MG_REG_MCTP_TX_BROADCAST_FIFO_FULL_OFFSET  17
#define HIPCIEC_AP_MG_REG_MCTP_TX_BROADCAST_FIFO_EMPTY_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_TX_BROADCAST_FIFO_EMPTY_OFFSET 16
#define HIPCIEC_AP_MG_REG_MCTP_TX_BROADCAST_ERR_CNT_LEN       16
#define HIPCIEC_AP_MG_REG_MCTP_TX_BROADCAST_ERR_CNT_OFFSET    0

#define HIPCIEC_AP_MG_REG_MCTP_RX_DISPATCH_P_RESP_FIFO_ERROR_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_RX_DISPATCH_P_RESP_FIFO_ERROR_OFFSET 18
#define HIPCIEC_AP_MG_REG_MCTP_RX_DISPATCH_P_RESP_FIFO_FULL_LEN     1
#define HIPCIEC_AP_MG_REG_MCTP_RX_DISPATCH_P_RESP_FIFO_FULL_OFFSET  17
#define HIPCIEC_AP_MG_REG_MCTP_RX_DISPATCH_P_RESP_FIFO_EMPTY_LEN    1
#define HIPCIEC_AP_MG_REG_MCTP_RX_DISPATCH_P_RESP_FIFO_EMPTY_OFFSET 16
#define HIPCIEC_AP_MG_REG_MCTP_RX_UNSUPPORTED_CNT_LEN               16
#define HIPCIEC_AP_MG_REG_MCTP_RX_UNSUPPORTED_CNT_OFFSET            0

#endif // __HIPCIEC_AP_MG_REG_REG_OFFSET_FIELD_H__
